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acpl-772l and acpl-072l 3.3v/5v high speed cmos optocoupler data sheet description available in either an 8-pin dip or so-8 style respectively, the acpl-772l or acpl-072l optocouplers utilize the latest cmos ic technology to achieve outstanding speed performance of minimum 25mbd data rate and 6ns maximum pulse width distortion. basic building blocks of this family of products are a cmos led driver ic, a high speed led and a cmos detector ic. a cmos logic input signal controls the led driver ic, which supplies current to the led. the detector ic incorporates an integrated photodiode, a high speed transimpedance amplifer, and a voltage comparator with an output driver. functional diagram features ? dual voltage operation (3.3v and 5v) ? allow level shifting functionality ? support high speed datarate of 25 mbd ? wide temperature operation ? cmos output and bufer input ? compatible with cmos and ttl logic level ? lower power consumption with 3.3v supply ? good ac performance with lower pulse width distortion ? lead-free option available specifcations ? 3.3v and 5v cmos compatibility ? high speed: dc to 25 mbd ? 6ns max. pulse width distortion ? 40 ns max. prop. delay ? 20 ns max. prop. delay skew ? 10 kv/ m s min. common mode rejection ? -40 c to 105 c temperature range ? safety and regulatory approvals: ul recognised - 5000v rms for 1 min. per ul1577 for acpl-772l for option 020 - 3750v rms for 1 min. per ul1577 for acpl-072l csa component acceptance notice #5 iec/en/din en 60747-5-2 C v iorm = 630 v peak for acpl-772l option 060 C v iorm = 560 v peak for acpl-072l option 060 applications ? digital fieldbus isolation: devicenet, profbus, sds ? multiplexed data transmission ? general instrument and data acquisition ? computer peripheral interface ? microprocessor system interface 8 7 6 1 3 shield 5 2 4 **v dd1 v i nc* gnd 1 v dd2 ** v o gnd 2 nc* i o led1 caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product * pin 3 is the anode of the internal led and must be left unconnected for guaranteed datasheet performance. pin 7 is not connected internally. ** a 0.1uf bypass capacitor must be connected between pins 1 and 4, and 5 and 8. truth table (positive logic) v i , input led1 v o , output h off h l on l
2 ordering information acpl-072l and acpl-772l are ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel ul 5000 vrms/ 1 minute rating iec/en/din en 60747- 5-2 quantity rohs compliant non rohs compliant acpl-772l -000e - 300mil dip-8 50 per tube -300e - x x 50 per tube -500e - x x x 1000 per reel -020e - x 50 per tube -320e - x x x 50 per tube -520e - x x x x 1000 per reel -060e - x 50 per tube -360e - x x x 50 per tube -560e - x x x x 1000 per reel acpl-072l -000e no option so-8 x 100 per tube -500e -500 x x 1500 per reel -060e -060 x x 100 per tube -560e -560 x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-772l-560e to order product of gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: acpl-072l to order product of small outline so-8 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. device selection guide 8-pin dip (300 mil) small outline so-8 acpl-772l acpl-072l
3 package dimensions acpl-772l 8-pin dip package acpl-772l package with gull wing surface mount option 300 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxv yyww date code 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) type number *option 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. option 060 code* 3.56 0.13 (0.140 0.005)
4 acpl-072l small outline so-8 package xxxv yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
5 regulatory information both acpl-072l and acpl-772l are approved by the following organizations: solder refow temperature profle note: non-halide fux should be used recommended pb-free ir profle note: non-halide fux should be used 217 ? c ramp-down 6 ? c /sec. max. ramp-up 3 ? c/sec . max. 150 - 200 ? c 260 +0/-5 ? c t 25 ? c to peak 60 to 150 sec. 20-40 sec. time w ithin 5 ? c of actual peak temperature t p t s prehea t 60 to 180 sec . t l t l t smax t smin 25 t p time temperature no tes: the time from 25 ? c to peak temperature = 8 minutes max. t smax = 200 ? c, t smin = 150 ? c 0 time (seconds) temperature ( ? c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 ?c 140 ?c 150 ?c peak temp. 245 ?c peak temp. 240 ?c peak temp. 230 ?c soldering time 200 ?c preheating time 150 ?c , 90 + 30 sec. 2. 5? c 0. 5? c/sec. 3? c + 1 ? c/ - 0 .5 ?c tight typical loose room temperature preheating rate 3? c + 1 ? c/ - 0 .5 ? c/sec. reflow heating rate 2. 5? c 0. 5 ? c/sec. iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01. (option 060 only) ul approved under ul 1577, component recognition program up, file e55361. csa approved under csa component acceptance notice #5, file ca 88324.
6 table 1. iec/en/din en 60747-5-2 insulation characteristics* description symbol acpl-772l option 060 acpl-072l option 060 units installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 vrms i C iv i C iv i C iii i C iv i C iii climatic classifcation 55/105/21 55/105/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 630 560 v peak input to output test voltage, method b** v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1181 1050 v peak input to output test voltage, method a** v iorm x 1.5=v pr , type and sample test, t m =60 sec, partial discharge < 5 pc v pr 945 840 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 4000 v peak safety-limiting values C maximum values allowed in the event of a failure, also see figure 2. case temperature input current output power t s i s, input p s, output 175 230 600 150 150 600 c ma mw insulation resistance at t s , v io = 500 v r io >109 >109 w * isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. surface mount classifcation is class a in accordance with ceccoo802. ** refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section iec/en/ din en 60747-5-2, for a detailed description of method a and method b partial discharge test profles. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. note: the surface mount classifcation is class a in accordance with cecc 00802. table 2. insulation and safety related specifcations parameter symbol value units conditions acpl- 772l acpl-072l minimum external air gap (clearance) l(101) 7.1 4.9 mm measured from input terminals to output termi - nals, shortest distance through air. minimum external tracking (creepage) l(102) 7.4 4.8 mm measured from input terminals to output termi - nals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 mm through insulation distance conductor to con - ductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 >175 v din iec 112/vde 0303 part 1 isolation group iiia iiia material group (din vde 0110, 1/89, table 1) all avago technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
7 table 3. absolute maximum ratings parameter symbol min. max. units storage temperature t s C55 +125 c ambient operating temperature [1] t a C40 +105 c supply voltages v dd1 , v dd2 0 6.0 volts input voltage v i C0.5 v dd1 +0.5 volts output voltage v o C0.5 v dd2 +0.5 volts average output current i o 10 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle please see solder refow temperature profle section table 4. recommended operating conditions parameter symbol min. max. units ambient operating temperature t a C40 +105 c supply voltages ( 3.3v operation) v dd1 , v dd2 3.0 3.6 v supply voltages ( 5v operation) v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2.0 v dd1 v logic low input voltage v il 0.0 0.8 v input signal rise and fall times t r , t f 1.0 ms table 5. electrical specifcations test conditions that are not specifed can be anywhere within the recommended operating range. the following specifcations cover the following power supply combinations: (4.5vv dd1 5.5v, 4.5vv dd2 5.5v), (3vv dd1 3.6v, 3vv dd2 3.6v), (4.5vv dd1 5.5v, 3vv dd2 3.6v) and (3vv dd1 3.6v, 4.5vv dd2 5.5v). all typical specifcations are at t a =+25 c , v dd1 = v dd2 = +3.3v. parameter symbol min. typ. max. units test conditions logic low input supply current [2] i dd1l 8.8 15 ma v i = 0 v logic high input supply current [2] i dd1h 1.4 5 ma v i = v dd1 output supply current i dd2l 4.3 10 ma i dd2h 4.5 10 ma input current i i C10 10 m a logic high output voltage v oh v dd2 -0.4 v dd2 v i o = C20 m a, v i = v ih v dd2 -1.4 v dd2 -0.4 v i o = C4 ma, v i = v ih logic low output voltage v ol 0 0.1 v i o = 20 m a, v i = v il 0.35 1.0 v i o = 4 ma, v i = v il
8 table 6. switching specifcations test conditions that are not specifed can be anywhere within the recommended operating range. the following specifcations cover the following power supply combinations: (4.5vv dd1 5.5v, 4.5vv dd2 5.5v), (3vv dd1 3.6v, 3vv dd2 3.6v), (4.5vv dd1 5.5v, 3vv dd2 3.6v) and (3vv dd1 3.6v, 4.5vv dd2 5.5v). all typical specifcations are at t a =+25 c, v dd1 = v dd2 = +3.3v. parameter symbol min. typ. max. units test conditions propogation delay time to logic low output [3] t phl 23.5 40 ns c l = 15 pf, cmos signal levels propogation delay time to logic high output [3] t plh 25.5 40 ns c l = 15 pf, cmos signal levels pulse width [4] t pw 40 ns c l = 15 pf, cmos signal levels maximum data rate [5] 25 mbd c l = 15 pf, cmos signal levels pulse width distortion [6] | t phl - t plh | |pwd | 2 6 ns c l = 15 pf, cmos signal levels propagation delay skew [7] t psk 20 ns c l = 15 pf, cmos signal levels output rise time (10% C 90%) t r 9 ns c l = 15 pf, cmos signal levels output fall time (90% - 10%) t f 8 ns c l = 15 pf, cmos signal levels common mode transient immunity at logic high output [8] | cm h | 10 20 kv/ m s v cm = 1000 v, t a = 25c, v i = v dd1 , v o > 0.8 v dd1 common mode transient immunity at logic low output [8] | cm l | 10 20 kv/ m s v cm = 1000 v, t a = 25c, v i = 0 v, v o < 0.8 v table 7. package characteristics all typical specifcations are at t a = 25 c. parameters symbol min. typ. max. units test conditions input-output momentary with-stand voltage [7,8,9] 072l v iso 3750 v rms rh 50%, t = 1 min, t a = 25c 772l 3750 772l with 020 option 5000 input-output resistance [9] r i-o 10 12 w v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz input capacitance [12] c i 3.0 pf input ic junction-to-case thermal resistance 772l q jci 145 c/w thermocouple located at center underside of package 072l 160 output ic junction-to-case thermal resistance 772l q jco 140 c/w 072l 135 package power dissipation p pd 150 mw notes: 1. absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. it does not guarantee functionality. 2. the led is on when v i is low and off when v i is high. 3. t phl propagation delay is measured from the 50% level on the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 4. the minimum pulse width is the shortest pulse width at which the specifed pulse width distortion is guaranteed. 5. the maximum data rate is the fastest data rate at which the specifed pulse width distortion is guaranteed. 6. pwd is defned as |t phl - t plh |. %pwd (percent pulse width distortion) is equal to the pwd divided by pulse width. 7. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions.
9 figure 1. typical propagation delays vs temperature figure 2. typical pulse width distortion vs temperature 15 17 19 21 23 25 27 29 31 -20 0 20 40 60 80 100 t a ( o c) t plh , t phl (ns) t plh t phl 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 -20 0 20 40 60 80 100 t a ( o c) pwd (ns) pwd figure 3. typical rise and fall time vs temperature figure 4. typical propagation delays vs load capacitance 4 5 6 7 8 9 10 11 12 -20 0 20 40 60 80 100 t a ( o c) t r , t f (ns) rise time fall time 20 22 24 26 28 30 32 15 25 35 45 55 c l (pf) t plh , t phl (ns) t plh t phl 8. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cml is the maximum common mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. 9. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 10. in accordance with ul1577, each acpl-072l is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 m a). each acpl-772l is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 11. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refers to your equipment level safety specifcation or avago technologies application note 1074 entitled optocoupler input-output endurance voltage. 12. c i is the capacitance measured at pin 2 (v i ). 0 1 2 3 4 5 6 15 25 35 45 55 c l (pf) pwd (ns) pwd figure 5. typical pulse width distortion vs load capacitance figure 6. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-2 surface mount so-8 product standard 8-pin dip product 0 200 400 600 800 1,000 0 25 50 75 100 125 150 175 t a - case temperature - c output power - ps, input current - is is (ma) ps (mw) 0 200 400 600 800 1000 0 25 50 75 100 125 150 175 t a - case temperature - c output power - ps, input current - is is (ma) ps (mw)
10 application information bypassing and pc board layout the acpl-x72l optocouplers are extremely easy to use. no external interface circuitry is required because acpl- x72l uses high speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 7, the only external components required for proper operation are two bypass capacitors. capacitor values should be between 0.01 m f and 0.1 m f. for each capacitor, the total lead length between both ends of the capacitor and power supply pins should not exceed 20mm. figure 8 illustrates the recommended printed circuit board layout for acpl-x72l. figure 7. recommended circuit diagram figure 8. recommended printed circuit board layout propagation delay, pulse-width distortion and propa - gation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from a low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. please see figure 9. figure 9. signal plot shows how propagation delay is defned pulse-width distortion (pwd) is the diference between t phl and t plh and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable. the pwd specifcation for acpl-x72l is 6ns (15%) maximum across recommended operating conditions. 7 5 6 8 2 3 4 1 gnd 2 c1 c2 nc v dd2 nc v o v dd1 v i 72l yyl c1, c2 = 0.01 f to 0.1 f gnd 1 v dd2 c1 c2 v o gnd 2 v dd1 v i gnd 1 c1, c2 = 0.01 f to 0.1 f 72l yyl input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos
figure 11. parallel data transmission example. propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. figure 11 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the acpl-x72l optocoupler ofers the advantage of guaranteed specifcations for propagation delays, pulse- width distortion, and propagation delay skew over the recommended temperature and power supply ranges. figure 10. propagation delay skew waveform as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 11 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumes to be clocked of of the rising edge of the clock. propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. if the parallel data is sent through a group of optocouplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at diferent times. if this diference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defned as the diference between the minimum and maximum propagation delays, either t plh or t phl for any given group of optocouoplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl and the longest propagation delay, either t plh and t phl . 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2010 avago technologies. all rights reserved. obsoletes av01-0462en av02-0324en - january 19, 2010

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